Tempest Character Symmetry and the "Z-Timing" Claim

ROM-level analysis of vector character geometry, AVG blanking architecture, and a replica PCB's asymmetric-character defect

Executive summary

A public post by a replica-PCB builder claims that original Atari color-vector hardware never drew a "perfect picture," illustrating the point with a letter "A" whose two legs differ visibly in length, and framing his board's matching behavior as faithful reproduction of "RGB Z timing" on original boards. This analysis tests that claim against the primary sources: the actual bytes of the Tempest vector ROMs, the Analog Vector Generator (AVG) architecture as modeled at the latch level in MAME, and decades of direct observation of original PCBs on Wells-Gardner 6100 monitors.

The finding is that the claim fails at every level. The character glyphs are defined mirror-symmetric in ROM, identically in both vector-ROM revisions. MAME applies no correction; it simply renders the coded endpoints. The original AVG architecture generates blanking (Z) and deflection from a single synchronous state machine, so the digital Z-versus-deflection skew the post describes cannot exist on original hardware. The residual analog effects that do exist are nanosecond-scale and produce endpoint dots and corner rounding, not leg-length asymmetry; critically, the beam physically never travels below the character baseline, so a "longer right leg" is geometrically impossible on an original board. A replica that re-derives Z and deflection through separate pipelines can create exactly this defect, and a production board exhibiting it has a design bug, not period-accurate behavior.

1. The claim under examination

The post asserts that the builder and a collaborator are "tweaking RGB Z timing to match original atari color vector pcbs... as close as possible all the way down to 1 clock cycle," then "tunning the analog section to match original hardware." It presents two renderings of the letter A: a symmetric one labeled "new pcb" and one with legs of visibly different lengths labeled "original pcb," and asks whether vectors should be "fixed" or replicated exactly — the premise being that original hardware displayed the asymmetric version.

Three questions decide the matter:

1. Does the Tempest code define characters with symmetric legs?
2. Does MAME (which displays them symmetrically) apply any correction?
3. Is there a timing mechanism on original hardware that would skew them anyway?

2. What the ROM actually encodes

The character set lives in the vector ROM ($3000-$3FFF on the 6502 bus). Each character is a subroutine of AVG short-vector (SVEC) opcodes, reached through the VGMSGA pointer table at $31E4, indexed by ASCVG character code (A = $16). The table entries are prebuilt JSRL opcodes; the entry for "A" resolves to vector address $3000.

Decoding the SVEC words with the authoritative latch semantics from MAME's avgdvg.cpp (5-bit two's-complement deltas: high byte = opcode + dy, low byte = intensity + dx) gives the following stroke list for "A":

$3000: SVEC dx= +0 dy=+16 lit    (0,0)  -> (0,16)    left leg, straight up
$3002: SVEC dx= +8 dy= +8 lit    (0,16) -> (8,24)    up-right to apex
$3004: SVEC dx= +8 dy= -8 lit    (8,24) -> (16,16)   down-right from apex
$3006: SVEC dx= +0 dy=-16 lit    (16,16)-> (16,0)    right leg, straight down
$3008: SVEC dx=-16 dy= +8 blank  (16,0) -> (0,8)
$300A: SVEC dx=+16 dy= +0 lit    (0,8)  -> (16,8)    crossbar
$300C: SVEC dx= +8 dy= -8 blank  (16,8) -> (24,0)    advance to next cell
$300E: RTSL

The glyph is exactly mirror-symmetric: both legs are vertical, both span y = 0 to 16, and both terminate on the same baseline. The letters H, M, N, and W decode the same way — all verticals span the full 0-24 cell height with no leg-length differences. The rev-3 vector ROM pair (136002-123.np3 + 136002-124.r3) and the rev-4/5 combined ROM (136002-138.np3) contain byte-identical character data.

Conclusion on question 1: confirmed. The source data defines symmetric, even legs. The "new pcb" rendering in the post is what the ROM encodes.

3. MAME applies no correction

MAME emulates the AVG at the state-machine level — the same latch strobes and opcode decoding the hardware PROM sequencer performs — and hands each vector's exact integer endpoints to its renderer. There is no compensation, filtering, or cleanup pass; MAME simply does not model analog settling at all. It looks symmetric because the data is symmetric. Conclusion on question 2: no correction exists to remove.

4. Why original hardware cannot produce the claimed skew

4.1 Z and deflection are one circuit, not two

In the AVG, drawing a vector works as follows: the state machine loads dx/dy into the DAC latches, then starts the vector timer (the 7497 bit-rate-multiplier chain). That single timer window gates both the integrator run (deflection) and the Z output (blanking). Beam-on and beam-move are two outputs of one clocked circuit. There is no independent Z pipeline whose latency could be tuned "down to 1 clock cycle" — alignment is exact to zero cycles by construction. Atari did not solve a Z-versus-deflection synchronization problem; the architecture defines it away.

4.2 The residual analog effects have the wrong shape and size

Downstream of the synchronous gate, each path has analog propagation delay: the Z amplifier chain is fast (nanoseconds to a couple hundred nanoseconds), while the deflection path lags behind ideal position because integrator op-amps and the WG6100 deflection amplifiers have finite bandwidth. But examine what those errors actually do to the "A":

• The entire outline is one continuous lit run. Z transitions exactly twice: beam-on at the bottom of the left leg, beam-off at the bottom of the right leg. A late beam-on clips a sliver off the start of the left leg. A late beam-off occurs after the state machine has already begun the next vector — the blanked move up-left toward the crossbar — so the beam draws a tiny tail in the new direction. It does not continue down the right leg's trajectory, because nothing drives the deflection that way anymore.
• The beam never travels below the baseline. The deflection drive reverses at (16,0); the geometry required to "extend the right leg" does not exist in the signal. The only mechanism that puts the beam below baseline is deflection-amplifier overshoot, which is small, ringing-shaped, and unrelated to Z.
• Deflection lag preserves segment lengths. The beam trails ideal position by a roughly constant group delay throughout a continuous run, so interiors and lengths are preserved; the visible residue is corner rounding at direction changes, symmetric between the two legs.

These are the classic vector-monitor artifacts — bright endpoint dots, faint comet tails at direction changes, rounded corners — and they are what healthy original boards actually show. At a 1.5 MHz AVG clock, one cycle is about 667 ns against strokes drawn over many microseconds; clock-granularity effects amount to a few percent of a leg. The post's illustration shows roughly 40-50 percent leg-length asymmetry, two orders of magnitude beyond anything the claimed one-clock matching tolerance could produce.

4.3 Empirical check

Decades of direct observation of original Tempest PCBs on WG6100 monitors: characters render symmetrically to the eye, exactly as the ROM defines them. This is the reference standard the replica claims to match, and it does not exhibit the artifact. Conclusion on question 3: no such mechanism exists on original hardware at visible magnitude, and the specific asymmetry shown (legs of different lengths) is geometrically impossible there.

5. Where the "timing consideration" actually comes from

The timing hazard only comes into existence when the board is rebuilt differently. If a replica re-derives Z and deflection through separate paths — for example, an FPGA reimplementation where the deflection DACs sit behind a pipelined or resampled interface while Z passes through a different register stage, or a modern DAC with multi-cycle latency the original monolithic DACs did not have — the designer has created precisely the race the original architecture precluded. Z then leads or lags deflection by whole clock cycles, the lit window slides relative to beam position, and the first and last strokes of every continuous lit run come out wrong: exactly the pathology of the "original pcb" illustration, and exactly the complaint now being fielded from a customer of the production board.

"Tuning the analog section to match original hardware" is, in isolation, a legitimate task: a replica's DACs, integrators, and Z driver are rebuilt from modern parts with different slew and settling, and matching the original's beam dynamics requires adjustment. But correct tuning converges on the original's appearance — symmetric characters with minor endpoint dots — not on an exaggerated asymmetry the reference hardware never displays.

6. Assessment of the post

The post is not fabricated from nothing; its author evidently understands the draw order well enough to predict which leg would shorten and which end would grow if Z timing were skewed. But the argument inverts cause and effect. The asymmetry is not an original-hardware characteristic that his board faithfully reproduces; it is a defect his redesign introduced, reframed as authenticity ("Atari color vectors never had a perfect picture to begin with"). The ROM data, the AVG architecture, the emulation evidence, and the field observation of original hardware all agree against him, and the customer complaint is the empirical confirmation: the replica is the outlier.

7. Remediation: how a replica should fix the skew

The fix principle is the one the original architecture embodies: do not minimize latency in either path — match the latencies. The original AVG has zero skew not because its paths are fast but because Z and deflection leave the same synchronous gate. A replica that broke that symmetry must restore it. Three tiers apply, depending on where the latency came from.

7.1 Quantify first

Use a two-channel scope: one probe on the X (or Y) deflection output, one on the Z/blank line, triggered on the start of a vector. Run a diagnostic pattern rather than game code — ideally a single lit stroke followed by a blanked retrace, repeated, giving a clean ramp with a Z edge at each end. Measure the offset between Z assertion and the ramp starting, and between Z deassertion and the ramp ending. Two diagnostics fall out immediately: if the offset is equal at both ends, the error is pure pipeline skew, fixable with a delay; if it differs, the analog stage also has slew or settling asymmetry. A square drawn clockwise versus counterclockwise is a useful visual check — pipeline skew makes the corner artifacts flip sides with draw direction.

7.2 The digital fix

Delay the blanking signal by the same number of clocks as the deflection pipeline. If the replica placed the DAC interface behind N register stages (an SPI serializer, a pipelined DAC, registered CPLD outputs where the original PROM sequencer was combinational), Z needs an N-stage shift register clocked by the same clock. The cleaner structural version is to re-time all outputs — DAC latch enables, integrator run window, Z — through one final register stage, restoring the original's one-circuit property so future edits cannot reintroduce skew.

7.3 The analog residual: the PWM-DAC case

PWM-as-DAC is the worst offender because the reconstruction filter is itself the deflection path's latency. A PWM output requires an aggressive low-pass to suppress carrier ripple, and that filter has group delay: a first-order RC with corner f_c contributes roughly 1/(2 π f_c) of passband delay — a 100 kHz corner is about 1.6 µs. If blanking is a direct digital output with near-zero delay, then against strokes drawn in roughly 10 µs, the deflection lags Z by some 15 percent of a stroke — the same class and magnitude of artifact as the uneven-legs illustration. This is corroborated empirically: an independent FPGA reimplementation of Asteroids Deluxe using on-chip PWM for the video DACs exhibited exactly this artifact class.

Three remedies, in ascending order of correctness:

1. Fixed digital delay on Z equal to the filter's low-frequency group delay (about 40 clocks at 25 MHz for the example above). Cheap and mostly sufficient; the residual is that first-order group delay is frequency-dependent, so fast and slow strokes compensate slightly differently.
2. Linear-phase filter plus fixed delay. Raise the PWM carrier — or generate sigma-delta at the FPGA clock rate, nearly free in fabric — so the filter corner moves well above the vector bandwidth, and use a Bessel alignment so group delay is flat. A single fixed Z delay then compensates all stroke speeds essentially exactly.
3. Give Z the same pipeline it is fighting. Where Z carries intensity levels (as on Asteroids Deluxe hardware), generate it as PWM or sigma-delta through a matched reconstruction filter — same topology, same corner, same group delay as X and Y. Matched latencies cancel identically, drift and tolerance track, and no delay is ever measured. This is the closest analog to the original design: identical paths cannot race.

Alternatively, dissolve the problem: an inexpensive SPI or parallel R-2R DAC has small, fixed, integer-clock latency and makes remedy 1 exact.

7.4 Diagnosis order for a discrete recreation

For a board that nominally clones the original schematic, skew should not exist at all, so the scope measurement doubles as an audit. If Z leads deflection by an integer number of state-machine clocks, registered logic was substituted where the original was combinational — a state PROM reimplemented in a registered CPLD or GAL is the classic case — and the fix is a compensating register on Z, or better, removing the added register to match the original. If the error is analog-shaped — the offset differs between stroke start and end, or scales with stroke speed — the substitute DAC or integrator op-amps settle differently than the originals, and "tuning the analog section" is for once the correct phrase: match integrator RC products and op-amp slew to the original's, or accept the substitute parts and add a matched delay on Z.

What does not work is the approach the post implies: measuring the digital timing to one clock, observing the picture is still wrong, and reclassifying the wrongness as authenticity. The residual was never in the digital timing — it is in the unmatched path latency, which one-clock digital matching cannot see.

Conclusion

The Tempest character set is defined mirror-symmetric in the vector ROM, byte-identically across ROM revisions, and MAME renders that geometry without correction. On original hardware, blanking and deflection are gated by the same synchronous timer, so digital Z-versus-deflection skew is structurally impossible, and the residual analog effects produce endpoint dots and corner rounding at nanosecond scale — never leg-length asymmetry, which the deflection geometry cannot generate at all. A replica board that displays uneven character legs has a Z-blanking bug of its own manufacture, most plausibly a pipeline misalignment between separately re-derived Z and deflection paths. The claim that this matches original boards is refuted by the primary evidence; the remaining open item is only which stage of the replica's Z path carries the misalignment, which requires the replica's own design files or a scope on the board to determine.